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\begin{document}
\date{}
\title{\Large\bf PAMS: Parallel Adaptive Memory Scheduling}
\author{\begin{tabular}[t]{c@{\extracolsep{5em}}c@{\extracolsep{5em}}c}
Yanpei Cao & Jiyang Li & Chang Lan\footnote{indicates equal contribution} \\
\\
\multicolumn{3}{c}{Department of Computer Science and Technology}\\
\multicolumn{3}{c}{Tsinghua University}\\
\multicolumn{3}{c}{Beijing, China 100084}\\
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\subsection*{\centering Abstract}
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Efficiently utilizing DRAM bandwidth is critical. Memory requests from different threads can interfere with each other. Existing memory scheduling techniques attempt to optimize the overall throughput obtained from DRAM and thus inter-thread interference is not the major consideration. As a result, concurrent threads can experience a performance collapse: one thread can be prioritized while another is starved by the scheduler.\\

We propose PAMS, a novel memory controller design that combines the ideas of \textit{thread ranking} and \textit{close-page}. Our memory controller ranks the threads with \textit{niceness values}. Subsequently, the controller's insertion shuffle algorithm reduces the time during which the least nice threads are prioritized over the nicest threads, ultimately resulting in less interference. Our results show that PAMS improves the performance, energy-delay product and performance-fairness product by 1-2\% compared to a close-page controller.\\

\section{Introduction}
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\section{Related Work}
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\section{Design Rationale}
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\section{Implementation}
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\section{Evaluation}
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\section{Conclusions}
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